Memory devices include a memory array with rows and columns of memory cells. The columns can be selected by column decoders and the rows selected by row decoders.
Architectures of address decoders made in a way substantially similar to what is described below are described, for example, in:    P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”, Kluver Academic Publishers, 1999, Chapter 5.2; and    G. Campardo, “Progettazione di memorie non volatili”, Franco Angeli 2002, pp. 199-205.